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Browse Prior Art Database

Channel Timer

IP.com Disclosure Number: IPCOM000036296D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Irwin, JW: AUTHOR [+2]

Abstract

A method is described in which a single logic timing mechanism is serially reused to provide all timings for a serial I/O channel including determination of transmission channel delays.

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Channel Timer

A method is described in which a single logic timing mechanism is serially reused to provide all timings for a serial I/O channel including determination of transmission channel delays.

As shown in Fig. 1, the channel operating state is used as an implicit stop control for the timer. The timer is reset and started by the channel whenever a frame is transmitted. If the timer is already running, it is reset and continues running. While operation is error-free, the timer never reaches a count that will activate the channel error controls because of periodic resets.

The timer is stopped without reset by the channel entering Stopped state, either because of task completion or an error. The current timer reading is then available to software until the next start com mand to the channel. Correct operation of the error compare circuits may be tested by diagnostic software by forcing errors and reading the timer contents.

As shown in Fig. 2, diagnostic software can measure the length of the channel wire or optical fiber by transmitting a frame that will cause an immediate Busy or Reject response by the channel hardware of the responding channel. By forcing such a hardware response, there is no software latency time included in the measurement. When the channel stops, software reads the timer and records the result as link physical latency for that channel.

After the physical latency is determined, diagnostic software transmits a frame that causes a software...