Browse Prior Art Database

Odd Even Interlace Detection Circuit

IP.com Disclosure Number: IPCOM000036301D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Brown, DJ: AUTHOR [+4]

Abstract

This disclosure describes a method of detecting when a circuit driving an interlaced CRT display is writing odd or even lines to the display. A delay to the line sync signal enables logic to distinguish between odd and even frames.

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Odd Even Interlace Detection Circuit

This disclosure describes a method of detecting when a circuit driving an interlaced CRT display is writing odd or even lines to the display. A delay to the line sync signal enables logic to distinguish between odd and even frames.

When a CRT display is being driven in interlaced mode, the driving circuitry will fill the screen alternately with odd and even lines of data (odd frames and even frames). During manufacturing test of such circuitry, it may become necessary to know which frame is being displayed.

For example, during the test of an adapter card the test pattern data being written to the screen is also written to a signature analysis circuit. The data written to the screen is interlaced so different signatures are obtained for odd and even frames. If card test signatures are to be compared with master signatures, it must be established whether the signature gathered was for the odd or even frame.

The circuit shown in Fig. 2 will solve this. Fig. 1 shows typical timing waveforms for Frame Sync (FS) and Line Sync (LS) signals. The circuit shown in Fig. 2 consists of two parts: a delay circuit to introduce a 2 ms delay to the line sync signal and a status bit latch. At the start of an even frame it will be set to a logic O, and at the start of an odd frame it will be set to a logic 1. If interfaced to a PC, as shown, the status bit can be read by an application program.

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