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Unique Wiring of a Very-High-Speed Clock

IP.com Disclosure Number: IPCOM000036311D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 78K

Publishing Venue

IBM

Related People

Stivers, DE: AUTHOR [+2]

Abstract

Disclosed is a solution for wiring a very-high-speed clock which neatly resolves six interrelated requirements to allow the creation of a multi-chip, very-high-speed processor. The solution is to distribute the clock wires by sharing the ground plane sandwiched between two voltage planes on a multi-layer card. Fig. 1 shows a typical clock (Image Omitted) wire distribution using a portion of the ground plane. Fig. 2 shows a cross section locating that ground plane in a multi-layer card.

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Unique Wiring of a Very-High-Speed Clock

Disclosed is a solution for wiring a very-high-speed clock which neatly resolves six interrelated requirements to allow the creation of a multi-chip, very- high-speed processor. The solution is to distribute the clock wires by sharing the ground plane sandwiched between two voltage planes on a multi-layer card. Fig. 1 shows a typical clock

(Image Omitted)

wire distribution using a portion of the ground plane. Fig. 2 shows a cross section locating that ground plane in a multi-layer card.

1. Electromagnetic Interference: A very-high-speed clock means shorter wavelengths. The clock wires used to deliver clock signal pulses from the clock chip to the other chips have the potential to become efficient radiators. By placing clock wires between the voltage planes on the top and bottom and by having the ground plane on the sides, the wires are shielded to minimize electromagnetic interference.

2. Parallel Connection: A separate wire goes from the clock chip to each of the other chips. This requires more wires than a serial connection, but this parallel connection allows each chip to get the clock signal pulse at the same time. Sharing the ground plane gives room for these additional wires.

3. Wire Length: A high-quality clock signal pulse at the receiving chip requires that the longest clock wire be kept to a specified maximum length. Once the longest clock wire length is established, the other clock wires must be made the same le...