Browse Prior Art Database

Memory Architecture Supporting Two 8-Bit/Pel Images or One 16-Bit/Pel Image

IP.com Disclosure Number: IPCOM000036315D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Flurry, GA: AUTHOR [+4]

Abstract

The architecture disclosed herein provides a selectable logical memory width so that the memory space can be used to store a single 16-bit/ pel image, or the memory array can be effectively split into two portions to allow storage of two separate 8-bit/pel images. The architecture also provides a secondary serial video port to allow easy access to the scanline pel data from either of the two 8-bit images or from the 16-bit image. (Image Omitted)

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 56% of the total text.

Page 1 of 2

Memory Architecture Supporting Two 8-Bit/Pel Images or One 16-Bit/Pel Image

The architecture disclosed herein provides a selectable logical memory width so that the memory space can be used to store a single 16-bit/ pel image, or the memory array can be effectively split into two portions to allow storage of two separate 8-bit/pel images. The architecture also provides a secondary serial video port to allow easy access to the scanline pel data from either of the two 8- bit images or from the 16-bit image.

(Image Omitted)

The memory architecture shown in Fig. 3 employs a memory array with one megabyte of storage. But a mode bit 1K/2K allows the memory space to be logically configured as one of two different widths, either one array which is 2048 X 512 X 8 or two arrays (banks) which are 1024 X 512 X 8. In the 1K mode two 8-bit/pel images can be stored, and in the 2K mode one 16-bit/pel image can be stored.

Fig. 1 shows how an 8-bit/pel image is stored in the memory arrays. The first number inside the boxes indicates the scan line, and the second number indicates the pel on that scanline. Outside of the memory unit boxes is labeled the corresponding row and column address for the memory units. Fig. 2 shows how a 16-bit/pel image is stored. The H and L indicate the high and low 8 bits of the pel.

(Image Omitted)

A physical diagram of the memory architecture is shown in Fig. 3. Block 2 in Fig. 3 converts an 18-bit linear address (linear update address lines) into a t...