Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Memory Organization for Graphics in a Virtual Memory Environment

IP.com Disclosure Number: IPCOM000036321D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 64K

Publishing Venue

IBM

Related People

Fogg, RG: AUTHOR [+3]

Abstract

A memory organization is described which allows graphic primitives to operate at high speed within a memory system by allowing the addresses to be restricted to a limited address range.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

Memory Organization for Graphics in a Virtual Memory Environment

A memory organization is described which allows graphic primitives to operate at high speed within a memory system by allowing the addresses to be restricted to a limited address range.

The C-Tile is a method of organizing a memory system so that the

(Image Omitted)

characteristics of dynamic read/write memories (DRAMs) can be used to facilitate the implementation of fast line-draw and area-fill algorithms. The C-Tile restricts addresses to a locality of the reference of updates for adjacent pixels except for those located on a C-Tile boundary. An additional benefit of organizing memory in this fashion is that hardware-assist logic used to perform the line draw, area fill and other graphics related functions can be used to operate on the entire main store address space. This means that the system can utilize the graphics-assist hardware to maintain hidden images.

Due to the increasing granularity of memories and the fact that these memories will be implemented in virtual address systems, a solution is required which can localize display references to single virtual pages and maintain the high line draw capabilities of addressing multiple pixels in a single memory cycle. Because of the locality of the reference attribute of the C-Tile, the number of page crossings and the associated Translate Lookaside Buffer (TLB) accesses are greatly reduced. Also, since this structure is implemented in system main store, the storage may be used for other purposes when not being used for display purposes.

The C-Tile is designed to use linearly organized storage and to make use of the static column mode of operation found in large-sized memory modules. The C-Tile organization can be applied to various sized tiles, but works best when applied to larger tiles. The example shown in Fig. 1 is a C-Tile applied to an eight-byte-wide memory and represents a 32 by 32-byte C-Tile with each pixel being one byte. Each Row Address (RAS) access to the storage now requires a single address translate to gain access to a 2048-byte page of memory; within this 2048-byte, 2KB page, one or two C-Tiles may be accessed. If the si...