Browse Prior Art Database

Wafer Strip Memory Packaging

IP.com Disclosure Number: IPCOM000036326D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Related People

Schrottke, G: AUTHOR [+2]

Abstract

This article describes the use of sections of memory wafers, typically strips, which contain multiple memory circuits rather than individual chips. These strips can be mounted to flexible carriers in several embodiments which will be described below. For simplicity, the Single In-line Package (SIP) configuration is shown. However, any of the various advanced memory packages mentioned above may be formed using the same basic idea.

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Wafer Strip Memory Packaging

This article describes the use of sections of memory wafers, typically strips, which contain multiple memory circuits rather than individual chips. These strips can be mounted to flexible carriers in several embodiments which will be described below. For simplicity, the Single In-line Package (SIP) configuration is shown. However, any of the various advanced memory packages mentioned above may be formed using the same basic idea.

Fig. 1 is used to demonstrate the concept. A section of the wafer, in this case a strip, is shown. Wiring for the circuitry is provided on a two-sided flex circuit, typically polyimide, but any of several materials can be used. The flexible carrier is C4 bonded to the appropriate pads on the wafer strip. The completed assembly is then bonded to a heat spreader, the material of which is chosen to match the TCE of silicon. The I/O pads for the system are brought out on the flexible carrier. A two-sided SIP can be formed by similarly

(Image Omitted)

attaching a second assembly to the other side of the spreader. The assembly is tested, and the lines of the non-working circuits may be cut using any one of several means, such as a laser.

Fig. 2 shows a similar wafer strip. In this case, the wiring is formed by the surface wiring provided during wafer processing. The I/O on the surface, accessible typically with C4 pads, may be attached to a flexible cable for connection to the next level of assembly.

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