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Processor Interface Method for the Functional Self-Test

IP.com Disclosure Number: IPCOM000036330D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

O'Dell, JT: AUTHOR

Abstract

The processor interface method described in this article provides a means for the address mapping of a test acquisition system within the address space of resident firmware and logic in order to implement functional self-test.

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Processor Interface Method for the Functional Self-Test

The processor interface method described in this article provides a means for the address mapping of a test acquisition system within the address space of resident firmware and logic in order to implement functional self-test.

A native functional self-test (FST) implementation is one in which the processor controlling the board under test is also the intelligent device conducting the test. An example of an EPROM implementation of the processor interface method is illustrated below.

The processor interface method consists of the following interfaces:
1. EPROM data, address, and ROM enable signals are

attached to the test acquisition system. The

manufacturing isolation test point (TPxx) and the

system read/write signals are also attached to the test

acquisition system.
2. The control and feedback portions of the test

acquisition system are memory mapped into the unused

memory locations of the EPROM.

The sequence of operation is as follows:
1. The test acquisition decode logic monitors the address

bus of the board under test and detects a test

acquisition system address.
2. The EPROM is de-selected using the manufacturing

isolation test point, and the test acquisition system

is enabled for transactions.

The advantages of this method include the following:
1. EPROM removal is not required.
2. The processor local bus demultiplexing and partial

address decode of the acquisition system are

automatically provided.
3...