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Efficient Data Wrap Testing Mechanism for Testing the I/O Adapter Interface Logic Within an I/O Processor

IP.com Disclosure Number: IPCOM000036331D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Keung, T: AUTHOR [+5]

Abstract

This article describes a data wrap testing mechanism for an input/output (I/O) processor (IOP) that requires no I/O adapter (IOA).

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Efficient Data Wrap Testing Mechanism for Testing the I/O Adapter Interface Logic Within an I/O Processor

This article describes a data wrap testing mechanism for an input/output (I/O) processor (IOP) that requires no I/O adapter (IOA).

Traditionally, for testing the IOA Interface logic within an IOP, one or more IOAs are required. These IOAs are located either on the same card or on a different card with the IOP being tested. An efficient data wrap testing mechanism that requires no IOA is disclosed herein.

The IOP consists of a microprocessor interface and storage con

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trol (MPS) chip, a system processor bus (SPB) interface chip and an I/O bus (IOB) interface chip. The IOB chip supports data transfer operations between the IOP and various IOAs.

To perform the testing of IOA interface logic of the IOB chip, a data wrap bit is added to the flags register of both the IOB and SPB chip. When the data wrap is set, the SPB chip will be in an IOA emulation mode, while the IOB chip will route data to/from (depends on read/write operation) the SPB chip instead of to/from an IOA.

Fig. 1 is a block diagram showing a data wrap for an IOA read operation test. For an IOA read from IOP test, test data is first loaded in the read buffer of the IOB chip. The data wrap bit of both IOB and SPB chip is set. The SPB chip then sends a read command to the IOB chip. The IOB chip will respond by sending the request data from the read buffer to the SPB chip. The test data...