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Fast Setting Master-Slave Data Bus Latch Using Depletion Load Master-To-Slave Coupling

IP.com Disclosure Number: IPCOM000036340D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Miller, CP: AUTHOR

Abstract

Disclosed is a data latch circuit which outputs an early latched data state ahead of the data bus latched state and further speeds the latching of data on the data bus. This circuit can improve device performance by reducing data path delays associated with long and/or high capacitance data buses in dense dynamic random-access memories (RAMs) and other types of semiconductor circuits.

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Fast Setting Master-Slave Data Bus Latch Using Depletion Load Master-To- Slave Coupling

Disclosed is a data latch circuit which outputs an early latched data state ahead of the data bus latched state and further speeds the latching of data on the data bus. This circuit can improve device performance by reducing data path delays associated with long and/or high capacitance data buses in dense dynamic random-access memories (RAMs) and other types of semiconductor circuits.

Fig. 1 shows a data latch circuit comprised of master latch components T4 through T7 sized appropriately for the data bus load, depletion devices T8 and T9, and slave latch devices T1 through T3. The master latch devices are not directly steered by external data bus nodes DL and DR but by the more lightly loaded internal nodes SDL and SDR. The slave latch is sized to set and latch internal nodes SDR and SDL at a much higher rate than the master data latch. Signal is provided to internal latch nodes SDR and SDL through depletion devices T8 and T9. When the rate of signal development is slow, which is typical of loaded bus data, devices T8 and T9 can be sized to provide isolation between internal latch nodes SDR and SDL and the data bus without reducing the signal to the internal nodes.

Referring to the timing diagram in Fig. 2, following signal development time SDT, signal DLSP makes a positive transition during latch time LT. The slave latch sets quickly, permitting internal nodes SDR and SDL to...