Browse Prior Art Database

Reducing Instruction Cache Reload Latency

IP.com Disclosure Number: IPCOM000036354D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Hardell, WR: AUTHOR [+2]

Abstract

Disclosed is a means to reduce Instruction Cache reload latency by varying the pattern of unloading a memory data buffer used for reloads.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Reducing Instruction Cache Reload Latency

Disclosed is a means to reduce Instruction Cache reload latency by varying the pattern of unloading a memory data buffer used for reloads.

This scheme is for a system in which the memory data bus width is twice the width of the I-Cache reload (I-reload) bus. Because the memory bus is twice as wide as the I-reload bus, the data must be buffered before it is sent to the I- Cache.

The I-Cache will receive only half the first memory data immediately. The other half will be delayed a cycle. In this scheme either half of the memory data can be sent to the I-Cache first.

In this scheme the I-Cache will receive the data that it needs first. By having the capability to select the pattern of sending data to the I-cache unit, overall I- cache reload latency is reduced by an average of .5 cycle.

In the example given below the memory bus will be one quad-word wide and the I-reload bus will be one double-word wide. A total of four quad words are read from memory. Eight transfers will be required to send this data to the I- Cache. This is shown in the figure. The two sequences are also shown in the figure. In the first sequence double word 0 is sent first. In the second sequence double word 1 is sent first.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]