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Quick Memory Test of a Bit-Steering Spare Bit

IP.com Disclosure Number: IPCOM000036356D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Hardell, WR: AUTHOR [+2]

Abstract

Disclosed is a means to quickly test the bit-steering spare bit while testing the normally used random-access memory (RAM) data bits. The separate (and additional) memory test does not have to be performed to test the spare bit.

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Quick Memory Test of a Bit-Steering Spare Bit

Disclosed is a means to quickly test the bit-steering spare bit while testing the normally used random-access memory (RAM) data bits. The separate (and additional) memory test does not have to be performed to test the spare bit.

Bit-steering (sometimes referred to as bit-sparing) is a method for logically replacing a bad memory column with a good (spare) memory column. The spare bit position can logically replace any one of the data or check bits.

Normally, the processor can use the error correction code (ECC) logic to verify the memory by writing a data/check bit pattern to the memory and reading back the data. The data and check bits are tested using the ECC logic. However, the ECC logic can detect an error condition for the data bit and check bit locations only. The spare bit cannot be checked by standard ECC logic without bit-steering being enabled. In this test the ECC error is flagged to the processor by an interrupt.

A more crude way to test all of the memory bits is to:

1) run a test on the data and check bits,

2) steer the spare bit into one of the original

data/check bit positions, and

3) rerun the test with the spare bit replacing one of

the original bits.

The memory test method described herein eliminates steps 2 and 3 above. In this method the spare bit is tested at the same time as the other bits as follows: 1) When writing the data to memory, data bit 0 (D0)

is written into its location and, also, into...