Browse Prior Art Database

Multi-Port Data Cache Directory

IP.com Disclosure Number: IPCOM000036359D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Awad, J: AUTHOR

Abstract

The data directory is used to hold the address for the data stored in the data cache. In a typical environment such as the 9370 MOD 60, one processor unit is allowed at any one time. This may be the CPU or the I/O processor. In order to handle the I/O, a synchronization mechanism was designed, which usually shuts down the processor access to cache for a few cycles regardless of whether the I/O has any data in (Image Omitted) cache or not. A two-port read directory will allow the I/O to peek at the directory without shutting down the CPU unless I/O data is in cache.

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Multi-Port Data Cache Directory

The data directory is used to hold the address for the data stored in the data cache. In a typical environment such as the 9370 MOD 60, one processor unit is allowed at any one time. This may be the CPU or the I/O processor. In order to handle the I/O, a synchronization mechanism was designed, which usually shuts down the processor access to cache for a few cycles regardless of whether the I/O has any data in

(Image Omitted)

cache or not. A two-port read directory will allow the I/O to peek at the directory without shutting down the CPU unless I/O data is in cache.

The same two-port read directory could be used for a dual-stream processor by multiplexing the I/O and the auxiliary processor on one address, and the primary processor on the other address port. Another use for this proposal would be to allow the instruction processor and the execution processor to access the data cache simultaneously.

A 2-port directory would be implemented to receive the CPU address and the I/O address simultaneously. Fig. 1 shows a timing diagram of the existing 9370 MOD 60 sequence of operation.

By having 2-port read directory, and possibly a 2-port read cache, two units could be reading the cache at the same time. On a cache write, then one unit will be allowed to write the cache at any one time.

Fig. 2 shows a case where an I/O is peeking at the data cache but does not transfer any data.

Fig. 3 shows a case where an I/O is peeking at the data cach...