Browse Prior Art Database

Method of Assuring a Two-Cycle Start, Zero-Cycle Stop, Non-Chopping on Chip Clock Control Throughout a VLSI Clock System

IP.com Disclosure Number: IPCOM000036361D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Jones, L: AUTHOR [+3]

Abstract

In previous generations of processors a clock generation function was typically performed at a central location and clocking signals were distributed, as required. The clock controls and start/stop conditions were also located at this central location.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

Method of Assuring a Two-Cycle Start, Zero-Cycle Stop, Non-Chopping on Chip Clock Control Throughout a VLSI Clock System

In previous generations of processors a clock generation function was typically performed at a central location and clocking signals were distributed, as required. The clock controls and start/stop conditions were also located at this central location.

With the advent of VLSI, a great deal more logic is present on a single logic chip and there are significant advantages to placing clock generation and control on the logic chip. Likewise, the clocking requirements have changed to a significant degree which requires new distribution and control methods. In some cases, the central function which generates common clock control signals may be located on a single chip separate from the chips where clocks are generated and the actual gating takes place. When generating these final gating signals, the variation in the distribution of the common control signals must be accounted for to ensure that the clocks are started and stopped uniformly across an entire system without chopping or slivering any clock pulses. This invention describes a method for generating a set of control signals which meet these goals.

The Racetrack II System has developed a Clocking Subsystem which will develop all of its clocks on the final logic chip. An oscillator and delayed oscillator will be delivered to each chip and these signals will be the basis for clock development. A clock macro is present on each chip and will be utilized to generate a controlled latch clock (C1) and trigger clock (C2). A set of free- running clocks will be used to interrogate a control line to sequence the controlled system clocks on and off.

This invention is based on the method of interrogating a basic control signal (Clock Run) to provide the shortest stop cycle, a synchronized start cycle, and to guarantee full clock periods (i.e., no

(Image Omitted)

clock chopping during these cycles). This provision is at the chip level. The control of this chip input is a centralized function at both the card and board levels.

The Clock Run line is propagated, from the on-card central control, synchronized to the leading edge of a C2 clock. This propagation will guarantee delivery to each chip on the card in sufficient time to be latched at the following C1 time. The circu...