Browse Prior Art Database

Hardware Alignment

IP.com Disclosure Number: IPCOM000036365D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Awad, J: AUTHOR

Abstract

The conventional cache of the IBM 9370 MOD 60 has a fixed layout with a 4-byte even boundary. This limited the interface to the processor to a single word. This cache had a 1k x 4-byte organization. However, in a 370 environment, most data transfers use an 8-byte boundary, starting at any byte in the line of data. This implies a multi- cache cycle on stores and fetches (up to 3 cycles). (Image Omitted)

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Hardware Alignment

The conventional cache of the IBM 9370 MOD 60 has a fixed layout with a 4- byte even boundary. This limited the interface to the processor to a single word. This cache had a 1k x 4-byte organization. However, in a 370 environment, most data transfers use an 8-byte boundary, starting at any byte in the line of data. This implies a multi- cache cycle on stores and fetches (up to 3 cycles).

(Image Omitted)

If the cache is organized as 512 x 8 bytes and the CACHE/CPU interface is increased to an 8-byte interface, then any 8 bytes could be accessible to the processor in one cache cycle. This design will boost performance of the 9370/60 by achieving hardware alignment across a given line boundary, and the cache will automatically have the capability of an 8-byte interface to storage.

If the processor needs 8-bytes starting at byte 2, in the old design, it requires up to three cycles to obtain them (Fig. 1). In the new organization, each cache unit will have its own address port. When receiving an address from the CPU, it is automatically incremented by one.

Fig. 2 shows eight separate arrays. Each array is 512 x 9. Once the address is generated, a multiplexer drives the proper address to the array, and then the proper byte is steered to the DATA-BUS. With this setup, if the processor needs 8-bytes starting at byte 2 in the data line, only one access cycle is needed. This is done by presenting both the address, and the address incremented by one, to t...