Browse Prior Art Database

Branch Command for a Hardware Simulation Accelerator

IP.com Disclosure Number: IPCOM000036366D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Fogg, RG: AUTHOR [+2]

Abstract

Disclosed is a more flexible branch instruction concept to be used in a hardware simulation engine.

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Branch Command for a Hardware Simulation Accelerator

Disclosed is a more flexible branch instruction concept to be used in a hardware simulation engine.

The traditional conditional branch command uses a fixed set of branch conditions on a fixed set of flags. In a simulation environment either more flags or different conditions may be required than were conceived when the hardware was designed. This invention provides a much more flexible set of flags and conditions.

The disclosed conditional branch command uses the result of a modified gate evaluation. Two of the four input operands in the branch command point to any two nodes in the Current State Array, the other two operands holding the branch address. A normal gate evaluation is done on these nodes, using the function table to generate a result. A zero resut indicates a branch condition; any other state will not branch. Since the function table is programable, any function of two operands can be used. This allows an unlimited number of flags to test with any conceivable conditional test.

This flexible branch stratagy can be exploited in many ways. A few examples are given below.

1) Wait for host response. When the host is sent a packet which requires a response, a flag (node) is set. As many gates as can be evaluated without the host response are executed, then a conditional branch is put in the model to force the hardware to wait for the host to reset the flag. When the flag is cleared, the hardware continues...