Browse Prior Art Database

Reconfigurable Current State Array for a Hardware Simulation Accelerator

IP.com Disclosure Number: IPCOM000036368D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Montoye, RK: AUTHOR [+3]

Abstract

This invention provides a way to trade off model size against run speed in a simulation engine. The simulation engine described performs a hardware evaluation of a four-input gate. The concept can be extended to gate with any number of inputs.

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Reconfigurable Current State Array for a Hardware Simulation Accelerator

This invention provides a way to trade off model size against run speed in a simulation engine. The simulation engine described performs a hardware evaluation of a four-input gate. The concept can be extended to gate with any number of inputs.

For maximum speed the hardware uses four identical arrays for input data so that each of the four operands can be fetched simultaneously. For a given design the maximum model size is set by the amount of memory in each source array. By reconfiguring the memory, a model larger than the size of an individual array can be simulated. The maximum model size can be doubled by logically pairing two sets of arrays to generate two arrays twice the size of an individual array. The price for this is that the simulation speed is halved because it now takes two cycles instead of one, to fetch the four operands. The model size can be doubled again by treating the four arrays as one large array, again halving the simulation speed.

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