Browse Prior Art Database

CI Bus Load/Store Fast Path

IP.com Disclosure Number: IPCOM000036386D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Bailey, RN: AUTHOR [+3]

Abstract

Disclosed is a circuit for providing a fast path for load and store data of 4 bytes or less to the Channel Controller (CC) chip. This circuit improves system performance by not buffering all loads and stores while providing support for load and stores of up to 128 bytes.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 56% of the total text.

Page 1 of 2

CI Bus Load/Store Fast Path

Disclosed is a circuit for providing a fast path for load and store data of 4 bytes or less to the Channel Controller (CC) chip. This circuit improves system performance by not buffering all loads and stores while providing support for load and stores of up to 128 bytes.

The processor supports many load and store formats. The processor may choose to perform traditional loads and stores using 32-bit registers, or it may do store multiples of up to 64 bytes, or store strings of up to 128 bytes. Since the processor is capable of providing the CC chip with data faster than it can pass it on to the attached Serial Link Adapters (SLAs), a buffering scheme is necessary to control the flow of data. Please see Figs. 1 and 2. Note the 64-bit data bus coming into the CC chip with a 16-bit data bus leaving the CC chip and going to each SLA. As shown in Fig. 1, each CC chip is capable of supporting up to 4 Serial Link Adapters.

The CC chip thus provides a buffer to hold the maximum possible data that can be sent by the processor. A 128-byte buffer is provided by the design to handle the longest possible string operation. This buffer, however, adds latency to the data transfer process since the data must be received from the SIO bus before it can be passed on to the CI bus. After the data is in the buffer, it is then put on the CI bus 2 bytes per cycle. Buffer latency is acceptable on transfers of many bytes, as it is required to match the wide SIO...