Browse Prior Art Database

Register File With System Logout

IP.com Disclosure Number: IPCOM000036397D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Brantley, WC: AUTHOR [+8]

Abstract

In many VLSI applications, there is a need for small local stores. However, previous designs of such storage units embedded in the logic of a chip typically suffer from chip testability difficulties and a lack of system logout capability. If the unit is designed as a small random-access memory (RAM), for instance, the logic must be specially configured to provide test access at neighboring shift register latches (SRLs) - at a design cost. Such designs are not capable of system logout. This disclosure describes a register file, which is in itself 100% level sensitive scan design (LSSD) compatible that also deploys the scan strings as tools to provide system logout and selective storage alteration. The Solution

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Register File With System Logout

In many VLSI applications, there is a need for small local stores. However, previous designs of such storage units embedded in the logic of a chip typically suffer from chip testability difficulties and a lack of system logout capability. If the unit is designed as a small random-access memory (RAM), for instance, the logic must be specially configured to provide test access at neighboring shift register latches (SRLs) - at a design cost. Such designs are not capable of system logout. This disclosure describes a register file, which is in itself 100% level sensitive scan design (LSSD) compatible that also deploys the scan strings as tools to provide system logout and selective storage alteration. The Solution

The disclosed register file is a high speed, high density design. Each storage location is implemented as one of the two latches of an SRL (either a master or slave). It is therefore completely LSSD compatible by design and is not subject to the one-to-one correspondence

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restraints placed on normal embedded RAMs. Also, by this design, test generation is eased, as the SRLs serve as test points - providing a 100% testable structure. In system use, there is a need for more slave latches (driven by the slave clock). To accomplish this, some of the LSSD master latches reconfigure into slaves. Table I shows the various configurations. Fig. 1 shows how the register file looks in the system mode. Fig. 2 shows the LSSD mode. Finally, Fig. 3 shows the logic utilized to enable the features described. Scan Modes

There are two means of reading (scanning) register file contents. In LSSD test mode, all latches are connected into one shift register

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string. Scan is accomplished by successively pulsing the A and B clocks.

Development of the Scan Mode: A separate system scan mode (as opposed to chip test scan mode) was developed to enable selective reading and writing of register file locations without destructive shifts within the files. The underlying idea is to set enables, selects and data for the register file by scanning techniques (with the scanning clocks turned off inside the register file) so that normal operation clocking will perform the desired read or write. If the register file data is read, it is stored in the output register, which can be scanned (again, with the

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register file scanning clocks turned off) to an output pin. If a file location is to be written into, its enable line is preset high so that normal clocking will set it. In Fi...