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Scanning a Chip Under the Control of an Asynchronous Slow Clock of a Support Processor

IP.com Disclosure Number: IPCOM000036417D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 57K

Publishing Venue

IBM

Related People

Jaber, TK: AUTHOR

Abstract

Consider a chip that needs to be scanned out by an external support processor. The support processor has access to a one-scan input pin and a one-scan output pin and is operating on a clock that is slower and asynchronous with respect to the chip clocks. The support processor does not have any control over the chip clocks and needs to scan in/out one and only one bit of data into/from the chip scan strings every time its asynchronous clock completes a clock pulse.

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Scanning a Chip Under the Control of an Asynchronous Slow Clock of a Support Processor

Consider a chip that needs to be scanned out by an external support processor. The support processor has access to a one-scan input pin and a one- scan output pin and is operating on a clock that is slower and asynchronous with respect to the chip clocks. The support processor does not have any control over the chip clocks and needs to scan in/out one and only one bit of data into/from the chip scan strings every time its asynchronous clock completes a clock pulse.

This is a typical problem encountered during debug operations. Often during debug, there is a need to read the state of the chip SRLs, and because of pin limitations, one pin is available as a scan- in pin and one pin as a scan-out pin.

The solution is threefolds:

1. to be able to connect all scan strings into a long

scan string comprising all shift register latches

(SRLs) on the Chip (except the SRLs supporting

debug),

(Image Omitted)

2. to be able to scan in/out one and only one bit of

data for every pulse of the support processor's

slow asynchronous clock without having to use the

chip clocks, and

3. to keep the chip in a Hold state (logic frozen)

until the support processor relinquishes control

of it.

To achieve the solution, a requirement must be imposed on the chip design allowing for a Hold port on every SRL in the chip (except for the three SRLs shown in Fig. 1 which control the shift operation).

If the chip...