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Ce Controlling Chip Scan Strings for Self-Test, LSSD and Debug Tests

IP.com Disclosure Number: IPCOM000036426D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 69K

Publishing Venue

IBM

Related People

Jaber, TK: AUTHOR

Abstract

This article describes a piece of logic that allows the control of various chip scan string configurations to be consolidated into an n- bit multiplexing logic, where n is the number of chip scan strings. (Image Omitted) (Image Omitted) Background

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This is the abbreviated version, containing approximately 56% of the total text.

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Ce Controlling Chip Scan Strings for Self-Test, LSSD and Debug Tests

This article describes a piece of logic that allows the control of various chip scan string configurations to be consolidated into an n- bit multiplexing logic, where n is the number of chip scan strings.

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Background

With chip self-test becoming a preferred choice for VLSI chip/ wafer testing, and Level-Sensitive Scan Design (LSSD) chip/wafer testing still the adopted testing technique for many of the VLSI chips, and with the need to limit the chip/tester interface pins to less than 256, which is what the VLSI chip testers can handle at the present time, chip scan strings need to conform to configurations imposed by the various test operations.

Test Requirements:

1. For self-test operations, the scan strings need to be configured into a Self-Test Using Multiple Parallel Signatures (STUMPS) mode (Fig. 1).

2. For LSSD testing, the scan strings should be independent and accessible to the tester via primary scan inputs and primary scan outputs.

3. For inter-chip wiring test, each chip I/O pin (except clocks) has a Shift Register Latch (SRL) associated with it. Those SRLS connected together form one or more Boundary scan string(s). Those scan strings are similar to any scan string on the chips. However, during the inter-chip wiring test, they must be configured into one scan string with access to the first SRL in the string from a chip Primary Input (PI) and access to the last SRL in the string from a chip Primary Output (PO).

4. For reading and writing the state of all chip SRLS during debug operations, it is often desired to connect individual chip scan strings serially to form a long scan string comprising every SRL on the chip (card level debug). It is also desired that as the long scan string is being scanned out (read) by an external device, the data vector being read is also being rewritten so that the state of the chip is restored after being read. This is referred to as the wrap-back mode. Th...