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Fast Method for Generating Two-Bit ECC Errors for Testing

IP.com Disclosure Number: IPCOM000036428D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 5 page(s) / 50K

Publishing Venue

IBM

Related People

Arimilli, LB: AUTHOR [+2]

Abstract

Disclosed is a fast method for generating all possible two-bit errors for testing the error detection logic of a machine. This method relates to testing more efficiently the error detection logic of a design that uses an error correction code (ECC) to correct all single- bit errors and detect all double-bit errors. This testing can be done during the logic design process to test the accuracy of the design and (Image Omitted) can be put in IPL ROS (Initial Program Load - Read Only Storage) to test the machine every time it is IPLed prior to executing any system program.

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Fast Method for Generating Two-Bit ECC Errors for Testing

Disclosed is a fast method for generating all possible two-bit errors for testing the error detection logic of a machine. This method relates to testing more efficiently the error detection logic of a design that uses an error correction code (ECC) to correct all single- bit errors and detect all double-bit errors. This testing can be done during the logic design process to test the accuracy of the design and

(Image Omitted)

can be put in IPL ROS (Initial Program Load - Read Only Storage) to test the machine every time it is IPLed prior to executing any system program.

If N is the number of data bits plus the number of ECC bits, then the total number of possible one-bit errors is N. This does not cause a problem in testing the error correction logic of a design as N is not very large (usually under 100) and it does not take very much execution time to generate all the possible one-bit errors. But to generate all possible two-bit errors to test the error detection logic,
(N)C(2) combinations of two-bit errors are required, where:

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N)C(R) = N!/(R!(N-R)!) = number of combinations of picking R items at a time from a sample size of N. If N=40, then (N)C(2) = 780, which is a large number relative to 40 which corresponds to all possible one-bit errors. The problem is even more severe in machines that also use the address parity bit to generate the ECC, and, therefore, the actual number is 780 * 2 = 1560 unique cases to account for both values of the address parity.

The obvious method of generating the two-bit errors would be to alter one bit, for example, bit 0 (lsb) and hold this bit while consecutively altering bit 1 for the first word, then bit 2 for the second word, etc., and then starting over altering and holding bit 1 and

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consecutively altering bit 2 and then bit 3 for the next word, etc., until all combinations have been exhausted. See Fig. 1.

The program portion that generates errors in these bit positions, assuming that the bit before altering is 0, is given below. DO I = 0 TO 38

DO J = I+1 TO 39

ALTER "MEMORY(ADDR,I) '1'B"

ALTER "MEMORY(ADDR,J) '1'B"

ADDR = ADDR + 1

END END

1

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In the given code, MEMORY is a subroutine that alters memory and in parenthesis is the memory address and bit position to be altered. The total number of loops in this routine is the sum of 39 + 38 + 37 + ... + 1 = 780 which is also the total number of branches taken. The total

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number of instructions executed per loop is 3. This routine would have to be executed a second time with a different set of memory addresses to accomodate the two values the address parity can take (ECC computation also depends on address parity). Therefore, the total number of branches is 780 * 2 = 1560 and the total number of instructions executed is 3 * 1560 = 4680 of which (780 + 39) * 2 = 1638 are arithmetic operations (one addition operation for each incrementi...