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Decal With Power/Ground Plane Partitioned by Thermal Coefficient of Expansion

IP.com Disclosure Number: IPCOM000036438D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Katyl, RH: AUTHOR [+2]

Abstract

In the electronic packaging of semiconductor chips having controlled- collapse chip connector (C-4) pads to provide electrical connection to printed circuit cards, thermal expansion constraints are important because mounting the chip to an assembly must be done in a manner such that the thermal strains experienced during the usage of the device do not excessively fatigue the C-4 solder column and shorten its life. Also, mounting the chip carrier assembly must be done so that thermal strains do not shorten the life of the card-carrier connection, i.e., pins or solder joints. The use of a flexible chip carrier comprised of a thin polyimide film can flex to accommodate the thermal strain and provide long chip and joint life.

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Decal With Power/Ground Plane Partitioned by Thermal Coefficient of Expansion

In the electronic packaging of semiconductor chips having controlled- collapse chip connector (C-4) pads to provide electrical connection to printed circuit cards, thermal expansion constraints are important because mounting the chip to an assembly must be done in a manner such that the thermal strains experienced during the usage of the device do not excessively fatigue the C-4 solder column and shorten its life. Also, mounting the chip carrier assembly must be done so that thermal strains do not shorten the life of the card-carrier connection, i.e., pins or solder joints. The use of a flexible chip carrier comprised of a thin polyimide film can flex to accommodate the thermal strain and provide long chip and joint life. However, conventional thin film technology has no ground plane and only one signal plane, limiting its electrical capability in fan-out, delta-I noise and coupled noise.

The key to improving electrical performance is a power/ground (P/G) distribution plane. This plane is closely spaced from the signal plane with dielectric material. It provides low impedance connection of the chip power and ground terminals to the card which is needed to minimize delta-I noise during digital circuit clocking. Its close proximity to the circuit lines allows for minimum line-to-line coupling, reducing the problem of coupled noise between circuit lines. Coupled noise reduction is of parti...