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Browse Prior Art Database

Method for Making Bipolar Devices Within a Standard Complementary Metal Oxide Silicon Process

IP.com Disclosure Number: IPCOM000036449D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

El-Kareh, B: AUTHOR [+2]

Abstract

By adding three photo-masking steps to a complementary metal oxide silicon (CMOS) process, bipolar and field-effect devices of either polarity may be included in integrated circuits made by this BiCMOS process.

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Method for Making Bipolar Devices Within a Standard Complementary Metal Oxide Silicon Process

By adding three photo-masking steps to a complementary metal oxide silicon (CMOS) process, bipolar and field-effect devices of either polarity may be included in integrated circuits made by this BiCMOS process.

Referring to Fig. 1, the standard CMOS process is used to provide a P- layer 2 on P substrate 4 and to create shallow trenches 6 which are filled with an insulator, e.g., silicon dioxide (SiO2), and applying SiO2 layer 8. Then, by high energy ion implantation, deep N-doped region 10 is created and is normally used for forming N-wells in the CMOS process. The first of the three masks added to create this BiCMOS process is then used to block a low energy N-well implant in NPN bipolar structures, thus leaving layer 2 in a P- state. The region of layer 2 between trenches 6 becomes the base region of an NPN device and is tailored by a standard CMOS P-well implant.

The second of the three added masks is used to allow selective implantation to form P+ doping layer 11, as shown in Fig. 2, for the construction of collectors in PNP devices.

Referring next to Fig. 3, oxide layer 8 is removed and gate oxide layer 12 is grown and protected by polysilicon layer 14. The third mask of the three added to the CMOS process is used to define emitter contact region E and collector regions C while blocking CMOS gate and base ring regions B. This pattern and the processing to create the cross section shown in Fig. 3 is common to both PNP and NPN device regions. Exposed areas of layers 14, then 12 and finally trench-fill SiO2 6 are etched away. Intrinsic polysilicon 16...