Browse Prior Art Database

Retriggerable Monostable Multivibrator

IP.com Disclosure Number: IPCOM000036453D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Frushour, JE: AUTHOR

Abstract

A single shot multivibrator (MV) is configured with a retriggerable operational mode, which allows the MV to be retriggered while in its quasi-stable state. Preferably, the MV is implemented CMOS (Complementary Metal Oxide Silicon), so as to be particularly amenable for implementation in a densely populated logic chip, i.e., large-scale or very large-scale integrated (LSI or VLSI) circuitry.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

Retriggerable Monostable Multivibrator

A single shot multivibrator (MV) is configured with a retriggerable operational mode, which allows the MV to be retriggered while in its quasi-stable state. Preferably, the MV is implemented CMOS (Complementary Metal Oxide Silicon), so as to be particularly amenable for implementation in a densely populated logic chip, i.e., large-scale or very large-scale integrated (LSI or VLSI) circuitry.

For the sake of simplicity, the MV 10 is shown schematically (Fig. 1). A positive going pulse on either one of the inputs 1 and 2, of MV 10 (and more particularly of AND gate 3) generates a narrow pulse at the output 4 of NAND gate 5, when the other one of the inputs 1 or 2, as the case might be, is positive.

(Image Omitted)

The circuit of MV 10 is first described with the aid of the waveforms of Fig. 2 when operating not in its retriggerable mode. As such, prior to time t1 (Fig. 2), MV 10 is in its stable state, and the input level of signal -PGMSRT (waveform A) at input 2 is positive. At time t1, the input level of signal -CLR (waveform B) at input 1 goes positive. The resultant narrow pulse P at output 4 of gate 5 sets the output Q-not of LATCH 1 to its DOWN level L1D (cf. waveform D), causing the SWITCH to turn ON and setting LATCH 2. As a result, the output 6 of MV 10 (and more particularly of LATCH 2) is set to its DOWN level L2D (cf. waveform
F), thus placing MV 10 in its quasi-stable state. SWITCH and capacitor C are separate components that are not part of the integrated circuit (IC) chip not shown which includes the IC components of MV 10. The set input S of LATCH 2 will set even though the voltage Vc (cf. waveform E) from capacitor C at input - of COMPARATOR 2 is above the reference voltage Vlr (e.g., +3 volts) from a multi- level voltage reference source 7 having an output connected to the reference input + of COMPARATOR 2.

When the SWITCH turns ON at time t1, capacitor C begins to discharge from its quiescent voltage level Vs (e.g., +5 volts) with a time constant determined by R2 and C. COMPARATOR 1 compares the capacitor voltage Vc at its input + with the reference voltage V2r (e.g., +1 volt) provided at another output from source 7 which is connected to its input. At time t2, voltage Vc (waveform E) reaches the level V2r, and the resultant output from COMPARATOR 1 causes reset of LATCH 1 to its UP level L1U (waveform D). In response, the SWITCH turns OFF.

Capacitor C will now begin...