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Diagnosing On-Card Error Checking and Correcting Operations Using Latched Syndrome Data

IP.com Disclosure Number: IPCOM000036460D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 5 page(s) / 70K

Publishing Venue

IBM

Related People

Arlington, DL: AUTHOR [+3]

Abstract

The use of a wide system data bus can limit the number of control and error lines that exist at an interface of fixed physical size, i.e., memory card. A unique way to obtain error correction code (ECC) status data for diagnostics, requiring the monitoring of only a few error lines, is accomplished in the following manner.

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Diagnosing On-Card Error Checking and Correcting Operations Using Latched Syndrome Data

The use of a wide system data bus can limit the number of control and error lines that exist at an interface of fixed physical size, i.e., memory card. A unique way to obtain error correction code (ECC) status data for diagnostics, requiring the monitoring of only a few error lines, is accomplished in the following manner.

A large number of status registers are designed into an ECC/data flow chip. These status registers are multiplexed onto the system data bus during a special diagnostic cycle, eliminating the need for additional input/output to the bus. The latches are generally loaded and held during the same card operation that generates the active error state, and are generally read out by a subsequent diagnostic operation. The unique way in which the syndrome data is handled for ECC and extended error correction (XEC) diagnostics is the heart of this concept. The dedicated error lines for these status registers are: parity error line (PEL), corrected error line (CEL), ECC error line (EEL) and data valid (DVAL). PEL indicates if there was a parity error on one or more data bytes during a store, or on command and address bytes during any operation. The card also freezes certain critical card operations during this last condition.

CEL, EEL and DVAL are related to ECC and XEC. DVAL indicates to the system that the fetched data on the bus is valid. When a double bit fault is detected, XEC is invoked. ECC alone cannot correct the data, and DVAL remains inactive. This starts the internal XEC operation and allows it to be transparent to the system. When the XEC operation is complete, the line is forced active to indicate that the operation was successful and the data is valid, or to indicate that an uncorrected error exists. This is determined by the CEL and EEL lines. The card provides a unique feature related to the DVAL line. To prevent an unchecked situation where system performance is significantly degraded due to successive XEC operations, the DVAL line will be forced active on successive cycles of a multi-transfer fetch after an XEC operation has occurred. Storage operations must be completed in order for refresh to continue.

In general, the parity status register provides the location of the byte(s) associated with the bad parity. The check bit and redundant bit registers provide a way for the system to load and read the associated memory bits. A diagnostics routine can read the data bits over the data bus on one set of transfers and the check bits and redundant bits on the next set of transfers. The card identity bits provide a means for feeding data pertaining to the card's size and type to the system via the data bus. This data is based on card jumper positions and logic pin connections to the power planes.

The syndrome registers provide the most powerful on-chip diagnostics tool. These registers are read out in parallel over the data b...