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Execution Path Analysis for MLDVS Simulator

IP.com Disclosure Number: IPCOM000036491D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 34K

Publishing Venue

IBM

Related People

Yusti, CA: AUTHOR

Abstract

This article describes a technique to improve test case average verification for the mixed level design verification system (MLDVS).

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Execution Path Analysis for MLDVS Simulator

This article describes a technique to improve test case average verification for the mixed level design verification system (MLDVS).

MLDVS is a VM-based hardware simulator. The simulator is used to verify that a logic design functions correctly by applying stimuli to a representation of the logic and capturing the results. The ability to verify that the stimuli tests the model comprehensively can be enhanced by adding execution path analysis.

Execution path analysis alters the logic representation by adding flags after each conditional statement. The flags contain the name of the logic design, the type of conditional statement and where it appears in the design. The flags are set if during simulation, the conditional branch is taken based on the stimuli analyzing the flags that are set and not set allows the stimuli to be altered to more fully test the logic design. The drawing shows flow charts of the initial logic design and logic design with flags.

Functional hardware simulation can be described by a model that consists of three parts. The parts are the design under test, stimulus for the design under test (inputs) and the response (outputs) of the design under test.

The objective of simulation is to verify that a design always generates the correct response for all possible stimuli. This strategy is often impractical due to the large number of possible stimuli/responses and the time available for functional hardware simulation.

The objective instead becomes selecting a set of test cases that exercise the maximum possible function. Verifying the responses of these test cases will ensure the highest quality verification in the time available for simulation. The success of this strategy is based upon selecting the best test cases. The path trace algorithm assists in the selection process. Path trace is designed to work with a high- level design language. It is a data flow language used to describe a logic circuit design. MLDVS is a simulator which is used to functionally simulate logic designs.

The high-level desi...