Browse Prior Art Database

Two-Way Data Flow Interface Circuit to Increase Computer Processing Throughput

IP.com Disclosure Number: IPCOM000036495D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Padgett, R: AUTHOR

Abstract

A technique is described whereby two-way data flow is implemented in single data bus computer systems, which have only one data path, so as to increase data throughput. A data bus interface module is used to provide data path separation on the system input/output processor bus and the system input/output bus.

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Two-Way Data Flow Interface Circuit to Increase Computer Processing Throughput

A technique is described whereby two-way data flow is implemented in single data bus computer systems, which have only one data path, so as to increase data throughput. A data bus interface module is used to provide data path separation on the system input/output processor bus and the system input/output bus.

The two-way data flow interface circuitry, as shown in the drawing, consists of microprocessor 10, similar to the Motorola 68020, read-only storage (ROS) 11, random-access memory (RAM) 12, card interface module 13 and bus interface module 14.

Bus interface module 14 contains all required interface functions, a ping-pong buffer, byte alignment capability, master/slave direct memory access (DMA) control, in both the subsystem input/output bus and the internal storage of the system input/output processor, and multi plexed intercard bus, thirty-two bits wide, so as to attain the increased performance.

Card interface module 13 contains all interface circuitry controls, bus arbitration, interrupt arbitration, RAM controls, error correction controls (ECC), timer and timer controls, and an intercard bus control. The module also contains a microprocessor accessible only to cache and, if needed, can have a DMA first-in, first-out (FIFO) memory which would be utilized in burst mode only. The data flow paths are as follows:

Data path 1: Transfers between the microprocessor

(MP) bus and system input/output processor RAM

Data path 2: Transfers between the system

input/output processor RAM and the system input/output bus

Data path 3: Transfers between the MP bus and the

subsystem input/output bus

Data path 4: Transfers between the subsystem

input/output bus and the system input/output bus

Data path 5: Transfers between the subsystem

input/output RAM and the subsystem input/output bus

Data path 6: Transfers between the MP bus and the

system input/output bus

Both paths 1 and 4 are possible at the same time.

Data may be

read from, or written to the system input/output

processor RAM

at the same time data may be transferred between the

system

input/output bus and the subsystem input/output bus.

Both paths 2 and 3 are possible at the same time.

The Processor may be transferring data between the subsystem input/output bus at the same time a data transfer occurs between the system input/output bus and the system input/output processor RAM. Both data paths 6 and 5 are

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possible at the same time. The processor may be transferring data between the system input/outpu...