Browse Prior Art Database

Intel 82385 Snoop Diagnostic Circuit to Test Dma/Bus Master Snoop Cycles

IP.com Disclosure Number: IPCOM000036497D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 29K

Publishing Venue

IBM

Related People

Begun, RM: AUTHOR [+2]

Abstract

This article describes a method and hardware for checking the functionality of the cache invalidate interface between a system bus and the cache controller. It also provides a level of tag random-access memory (RAM) diagnostics not supported by an 82385 cache controller.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Page 1 of 3

Intel 82385 Snoop Diagnostic Circuit to Test Dma/Bus Master Snoop Cycles

This article describes a method and hardware for checking the functionality of the cache invalidate interface between a system bus and the cache controller. It also provides a level of tag random-access memory (RAM) diagnostics not supported by an 82385 cache controller.

The expedient disclosed herein provides a controlled method of testing the operation of the snoop function provided by the 82835 local bus interface. The snoop operation is important for maintaining cache coherency between the system memory and the cache data RAM. System bus master write operations must be tracked when accessing cachable system memory. The snoop diagnostic interface circuit of this disclosure adds very little hardware to the system. Its snoop diagnostic routine can be executed with or without memory in cachable memory space. It also provides a conclusive test of the internal tag RAM of the 82385. Each bit of the tag RAM can be turned on and off (one or zero) and confirmed without directly reading the tag RAM data. This is a significant improvement over the diagnostic coverage provided directly by the 82385. It only requires that the system memory have an enable/disable control and that the cachable memory space is programmable.

The hardware required to support the snoop diagnostic routine includes a bus master or direct memory access (DMA) capable of performing memory write operations to cachable memory space. In some personal computer systems the DMA controller provides such a function in the form of a DMA channel activated by a software request. Also, a flip-flop is required which has its clock input tied to a cache read miss signal (MISS1) from the cache interface. This signal is not the MISS signal from the 82385. The data input of the flip-flop is tied to supply voltage (Vcc) and the clear input is tied to an I/O port bit. The I/O port bit will be able to enable or disable/clear the read miss indication. The drawing shows the read miss indicator flip-flop and its connection to the system/cache interface.

The diagnostic routine which controls the operation of the hardware should reside in non-cachable memory space. The diagnostic routine consists of the following steps:

1) Disable and flush the cache. Disable/clear the read miss indication.

2)Turn off cache flushing and enable the cache.

3) The CPU will write 64k bytes of contiguous

cachable memory space with known data pattern.

4) Enable the read miss indicator.

5) The CPU will read the same 64k bytes of contiguous

cach...