Browse Prior Art Database

High Speed X.21 Circuit Switched Call Establishment

IP.com Disclosure Number: IPCOM000036506D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 4 page(s) / 51K

Publishing Venue

IBM

Related People

Polan, MG: AUTHOR

Abstract

This article describes a method which allows the establishment of X.21 circuit switched calls over high-speed lines. This is accomplished by eliminating the need for the immediate processing in real time by the CPU of each character of incoming Network Provided Information (NPI), and each outgoing selection signal character. Specialized X.21CS hardware is not required for its implementation.

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High Speed X.21 Circuit Switched Call Establishment

This article describes a method which allows the establishment of X.21 circuit switched calls over high-speed lines. This is accomplished by eliminating the need for the immediate processing in real time by the CPU of each character of incoming Network Provided Information (NPI), and each outgoing selection signal character. Specialized X.21CS hardware is not required for its implementation.

A Direct Memory Access Control (DMAC) is used to reduce both CPU load and real-time system requirements. Use of a DMAC allows much higher line speeds (closer to system bus speeds) during call establishment. Alternatively, a single CPU can manage many more communication lines concurrently.

Use of a DMAC during call establishment reduces the risk of receiver overrun and transmitter underrun conditions. (Receiver overrun occurs when previously received data is lost due to the arrival of new data. The CPU must read all received data from the USART before the arrival of any new data to prevent this condition. Transmitter underrun occurs when the CPU has not provided additional data to the USART before the USART has completed the transmission of all previous data.) Receiver overrun is typically the most significant real-time software restriction governing line speed.

System requirements for implementing this algorithm are:

Multiple interrupt and/or task level processing;

Universal Synchronous/Asynchronous

Receiver/Transmitter (USART)

supporting the MONOSYNC or BISYNC protocol;

Direct Memory Access Controller (DMAC) with a channel

that can

be used for USART transmit and receive;

The USART transmitter must provide for automatic

synchronization

character insertion during transmission;

The USART received must provide for automatic

synchronization

character deletion and parity error detection during

reception.

Software complexity can be considerably reduced with additional hardware (usually in the form of counters) which can detect certain X.21 states. However, a USART providing the ability to detect break and abort/idle conditions will suffice.

The difficulty in using a DMAC in the reception of NPI is the detection of the end of the NPI data transmission from the network. The key to overcoming this problem can be found in the format of the NPI data sent by the network. All valid data exchanged with the network during call setup contains ODD parity. Examinations of all allowable state changes (legal states that may follow X.21 CCITT states 6, 7 or 10) reveal that data containing EVEN parity will appear to be sent by the network following the NPI transmission. (An unsuccessful NPI

1

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exchange or an illegal state change will result in a local time-out of CCITT defined timers T2, T3A, T3B or T4B.) Based on this fact, the USART can be initialized to search for and report any EVEN parity condition while it is receiving NPI data. The USART will then automatically halt NPI data reception when the ne...