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XCU for Closely Shared L2 Lines

IP.com Disclosure Number: IPCOM000036516D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+5]

Abstract

In a multiprocessor configuration which is supported by a memory hierarchy involving a Write Through Write Allocate Exclusive (WTWAX) L1 cache per processor and two private Write Back (WB) L2 caches (which may be shared by multiple L1s), the Cross Interrogate (XI) represents a major factor in multiprocessor performance degradation.

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XCU for Closely Shared L2 Lines

In a multiprocessor configuration which is supported by a memory hierarchy involving a Write Through Write Allocate Exclusive (WTWAX) L1 cache per processor and two private Write Back (WB) L2 caches (which may be shared by multiple L1s), the Cross Interrogate (XI) represents a major factor in multiprocessor performance degradation.

A reduction in the XI penalty can be achieved by performing Cross-Cache Updates (XCU) for a class of stores that will update lines concurrently in both L2 caches. The naturalness of this approach is derived from the fact that in such a memory hierarchy the L2 is already updated on a double-word basis by the Write Through Activity for all of the lines stored into by the processors holding lines exclusively in their private L1 caches. The filtering of the set of stores seen by each L2 so as to determine which are candidates for XCU is based on identifying which lines are subject to close sharing and will likely be XIed in the future.

At the time of an XI the penalty for the XI for such lines which have been XCUed will be reduced by the line transfer time. This is replaced by a single "validation" cycle in the requesting L2.

Lines which are subject to multiple XIs are likely to be found in the directories of the both L2 but with the line invalidate in one directory as the result of a previous XI. In such a situation, the XI is handled normally but the line is marked as an XCU line in both L2 caches. The purpose of marking the line XC...