Browse Prior Art Database

Expandability of Tcw/Tag Memory

IP.com Disclosure Number: IPCOM000036524D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 94K

Publishing Venue

IBM

Related People

Dhawan, S: AUTHOR [+3]

Abstract

The I/O Channel Controller (IOCC) generates the MICRO CHANNEL* for the system. The IOCC chip contains the DMA controller that uses an 8-byte field, called a Tag, that contains the memory address, transfer length, the next Tag address and control information. The IOCC also translates the address generated by the bus master on the MICRO CHANNEL. The real memory address is contained in a 4-byte field called the Translation Control Word (TCW). For every 4Kbyte page there is one TCW.

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Expandability of Tcw/Tag Memory

The I/O Channel Controller (IOCC) generates the MICRO CHANNEL* for the system. The IOCC chip contains the DMA controller that uses an 8-byte field, called a Tag, that contains the memory address, transfer length, the next Tag address and control information. The IOCC also translates the address generated by the bus master on the MICRO CHANNEL. The real memory address is contained in a 4-byte field called the Translation Control Word (TCW). For every 4Kbyte page there is one TCW.

The Tag/TCWs are contained in external memory that can range from 128K bytes to 8M bytes. For cost reasons the external memory was chosen to be dynamic memory. This article describes a method to attach 128K bytes (64Kb X
4), 512K bytes (256Kb X 4), 2M bytes (1Mb X 4) and 8M bytes (4Mb X 4) to the IOCC. The external Tag/TCW memory has a 2- byte interface to the IOCC.

The row and column addresses are generated from the TCW/Tag address received by the IOCC from the processor or a Bus Master on the MICRO CHANNEL (the IOCC generates the MICRO CHANNEL). The TCW/Tag memory address mapping to the physical memory enables the memory controller in the IOCC to expand the TCW/Tag memory. The row and column addresses for the smallest memory size (128K bytes) are formed by using the upper and lower order address bits, as shown in Fig. 1. The additional row and column address bits for the larger memory modules are formed by alternating the row and column address bits.

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