Browse Prior Art Database

Two-Level Internal Bus Arbitration for the System IO Bus

IP.com Disclosure Number: IPCOM000036532D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 99K

Publishing Venue

IBM

Related People

Bailey, RN: AUTHOR [+3]

Abstract

Disclosed is a circuit for providing for a method of attaching three separate bus unit IDs to the System IO (SIO) bus, allowing each logical bus unit ID a partitioned level of bus arbitration within the functional partitions within each bus unit ID.

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Two-Level Internal Bus Arbitration for the System IO Bus

Disclosed is a circuit for providing for a method of attaching three separate bus unit IDs to the System IO (SIO) bus, allowing each logical bus unit ID a partitioned level of bus arbitration within the functional partitions within each bus unit ID.

The system IO chip consists of three logical partitions. Each partition is accessed by the processor as a bus unit ID. The three partitions are two Serial Linker Adapters (SLAs) and one IOCC. These three devices all require access to the SIO bus. This access is provided through a set of common logic that controls the SIO bus. Each device may make an asynchronous request for the bus resource, and the common logic will latch this request. Figs. 2 and 3 show a block diagram of this arrangement.

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When a bus grant is received from the SIO bus, the common logic passes the grant to the device that made the request. A fixed priority scheme is used to determine the arbitration results if more than one device requests at the same time. All requests received while the bus is granted to the device are latched by the common logic and will be processed in priority order with the next grant signal. See Fig. 3 for a logical block diagram of this circuit.

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Within each SLA there are three logical partitions: 1) load/store, 2) interrupts, and 3) DMA. Each of these partitions need to have access to the SIO bus. The same logic structure that is used in...