Browse Prior Art Database

Safeguard Mechanism for Critical Logic Security

IP.com Disclosure Number: IPCOM000036543D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 62K

Publishing Venue

IBM

Related People

Millas, RJ: AUTHOR

Abstract

This article describes a method and design for use in a processor system to safeguard an area of logic from accidental access.

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Safeguard Mechanism for Critical Logic Security

This article describes a method and design for use in a processor system to safeguard an area of logic from accidental access.

Very large-scale integration (VLSI) technology makes it possible to implement vast amounts of logic cells on a single module. This logic may contain several internal hardware-related registers and latches that are not usually accessed by the microprocessor. These internal registers and latches control the 'state' of the module.

Due to the complexity of these VLSI modules, it becomes important to obtain 'state' information via the microprocessor for debug pur-

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poses, whether during development or field support. Otherwise, the internal 'state' of the module may not be known. Also, the ability to alter the 'state' becomes another very valuable debug tool.

Straightforward access to this critical logic can be implemented, however, by accidental access that could modify the 'state' in an unwanted fashion and could result in a catastrophic unrecoverable error. For this reason these critical areas of logic should be protected from accidental access. This is becoming even more important, since microprocessor controller cards are now allowing software programs which used to reside within the host system to reside within the controller cards. This leads third party programmers to write code within the controller as well. This third party application code will be coexisting in the same storage as the hardware controlling microcode. If the 'state' is modified accidentally, it would most likely appear to be a hardware problem to the user.

A method and design to safeguard an area of logic from accide...