Browse Prior Art Database

Efficient Use of Digital Signal Processor Computational Power

IP.com Disclosure Number: IPCOM000036560D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 5 page(s) / 107K

Publishing Venue

IBM

Related People

Davis, GT: AUTHOR [+4]

Abstract

A technique is described whereby the operation of communicating digital processing systems is improved through the use of multiple circular buffers, so as to allow simultaneous transmission of data between interconnected systems. A cycle steal transfer is implemented, so that data from carrier interface circuitry can go directly into circular buffers, which are then used as delay line digital filters. (Image Omitted)

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Efficient Use of Digital Signal Processor Computational Power

A technique is described whereby the operation of communicating digital processing systems is improved through the use of multiple circular buffers, so as to allow simultaneous transmission of data between interconnected systems. A cycle steal transfer is implemented, so that data from carrier interface circuitry can go directly into circular buffers, which are then used as delay line digital filters.

(Image Omitted)

The concept provides four improvements:

1. Uses cycle steal transfer to load new data

samples into

the delay line of a finite impulse response

filter.

2. Provides circuitry to generate multiple circular

buffers,

one for each time slot on a carrier, so as to

effectively

demultiplex a bit stream.

3. Uses a synchronized channel counter as high-order

address

lines and uses frame counters as least

significant

address lines in order to point to the proper

buffer.

4. Uses channel numbers as the least significant

address

and the frame count as high-order addresses in

order to

handle as single high-speed bit stream without

separating

the channels.

Although the use of circular buffers is not new in digital processing systems, the improvement enables the circular buffers to be shared by interconnected processors. The concept increases the overall processing power of a system through the elimination of overhead instructions normally required for data transfers. The circular buffers, as used in this concept, are used not only as input data buffers, but also as a delay line for finite impulse response (FIR) filtering. The design enables input data to reside in one part of the circular buffer, while the program uses a trailing part of the buffer in its computations, thus avoiding the overhead of loading its delay line.

Typically, digital signal processor (DSP) requires a response to periodic synchronous interrupts, so as to read new data samples from input/output (I/O) subsystems. New samples are simultaneously written to the output portion of the I/O subsystem. After the I/O subsystem has been serviced, the DSP will take the new data samples from the input channels and load them into delay lines for FIR digital filtering. Although there are other applications where the new samples are

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used, the use of front-end FIR filtering is typical in most large class applications. In some applications, the I/O subsystem will buffer multiple samples, to minimize the interrupt overhead.

Cycle steal mechanisms have been used to transfer data samples to and from an I/O subsystem without the overhead normally associated with servicing an I/O subsystem. However, the buffer area is generally a special area of memory reserved just for I/O. The processor still had to move new data samples from the input buffer area into the delay line memory segment when a front-end filter was required. The concept described herein implements the cycle steal transfer into memory by eliminating...