Browse Prior Art Database

Dual Use of Pins to Output Internal Machine Status Information

IP.com Disclosure Number: IPCOM000036562D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 4 page(s) / 93K

Publishing Venue

IBM

Related People

Concha, F: AUTHOR [+2]

Abstract

This article describes a method of utilizing every available external bus of a multi-chip, microcode-controlled central processing unit (CPU) to relate its internal machine state when these external buses are idle or when their basic information is not required. This can bring important information to the very large-scale integration (VLSI) designer and architects to debug, fix internal problems, real-time test and, (Image Omitted) finally, to study the behavior of the machine while running application programs. The study of the machine internal behavior is used to augment performance of future designs. All this is achieved while minimizing any impact to packaging when the chip input/output (I/O) was multi-used.

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Dual Use of Pins to Output Internal Machine Status Information

This article describes a method of utilizing every available external bus of a multi-chip, microcode-controlled central processing unit (CPU) to relate its internal machine state when these external buses are idle or when their basic information is not required. This can bring important information to the very large-scale integration (VLSI) designer and architects to debug, fix internal problems, real-time test and,

(Image Omitted)

finally, to study the behavior of the machine while running application programs. The study of the machine internal behavior is used to augment performance of future designs. All this is achieved while minimizing any impact to packaging when the chip input/output (I/O) was multi-used.

This method uses two global techniques: first, the feedback of the information or modified information to the internal state machine controls for purposes of changing it, and, second, the external view of the machine state for debugging, testing and performance analysis.

Fig. 1 is an overall view at the two global techniques. The use of an external accessed register is shown with outputs that are fed back to the processor bus via a control point generated by the decoded processor microcode. The set of techniques to externally access key machine states of each VLSI chip as illustrated allow real-time testing and provide the information needed to alter the machine state transitions when required.

The CPU is controlled by a dual-phase clocking, as shown in Fig. 2, where a phase is used for function decoding and the other phase for execution of mainly processor bus accesses. This dual-phase clocking and the different CPU buses are used to implement the techniques.

The CPU's machine state is broadcasted via the control, storage, I/O and processor buses. Referring to Fig. 3 one of the control buses of the CPU is used to send information from the CPU instructions register field directly to the controls of the local storage. This information is only valid for the last micro-cycle of the previous instruction's execution phase. During any other execution phase and all de

(Image Omitted)

code phases, the same bus is used to pass information about the primary instruction buffer controls. This information includes instruction start, instruction buffer usages, execution of one cycle i...