Browse Prior Art Database

I/O Address Exception on the CI Bus

IP.com Disclosure Number: IPCOM000036575D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 70K

Publishing Venue

IBM

Related People

Bailey, RN: AUTHOR [+3]

Abstract

Disclosed is a method for detecting and reporting I/O address exeception conditions on address cycles to allow the processor to continue without having to wait for the entire I/O operation to complete.

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I/O Address Exception on the CI Bus

Disclosed is a method for detecting and reporting I/O address exeception conditions on address cycles to allow the processor to continue without having to wait for the entire I/O operation to complete.

The processor supports many load and store formats. The processor may choose to perform traditional load and stores using 32-bit registers, or it may do store multiples of up to 64 bytes, or store strings of up to 128 bytes. When the processor begins an I/O operation the I/O device asserts a lock line that holds the processor from executing any more instructions. In order to minimize the length of time that the processor is held up by an I/O instruction, the CC chip implemented a special CI bus protocol. Fig. 2 shows the overall block diagram of the system with the processor, CC Chip, and 4 SLA chips shown. The CI bus connects the CC chip with the SLA chips. The processor communicates with the CC chip over the SIO Bus.

In this protocol the address cycles are put out on the CI bus as soon as they have been received from the processor. This allows the addressed SLA to check the address and alignment of the data to make sure it conforms to its requirement while the rest of the data is coming into the CC chip from the processor. If an error is detected by the SLA, the error is reported by the CC chip to the processor while it is still locked. This allows the processor to determine which instruction caused the I/O address exeception....