Browse Prior Art Database

Mixed Technology Voltage Protection

IP.com Disclosure Number: IPCOM000036609D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

Ludwig, T: AUTHOR [+2]

Abstract

The development of increasingly aggressive technologies requires the use of lower power supply voltages to prevent breakdowns. The compatibility of older and more advanced technologies presents serious problems.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

Mixed Technology Voltage Protection

The development of increasingly aggressive technologies requires the use of lower power supply voltages to prevent breakdowns. The compatibility of older and more advanced technologies presents serious problems.

The proposed circuit scheme allows operating > 1 mm CMOS chips at 5 V and submicron CMOS chips at 3.4 V on the same bus without breakdown or reduced reliability.

The development of submicron and half-micron technologies requires an adapted power supply voltage Vh. The very thin gate oxide and the short channel of the transistors are unsuitable for Vh = 5 V. Therefore, the chips involved have to be operated at Vh = 3 to 4 V, with the value of Vh eventually settling at 3.4 V - 10%. Difficulties arise when the new technology has to fit a 5 V environment in which submicron chips have to communicate with older chips (see Fig. 1). The chips of the 5 V environment are TTL-compatible, and the most positive up-level MPUL of their drivers is 5.5 V. As this MPUL of 5.5 V would destroy the input/outut circuits of the new submicron devices, whose most allowable up-level MAUL is about 4.0 V, a circuit scheme is required which allows the two technologies to communicate without destruction.

The circuit of Fig. 2 includes a well-known CMOS driver circuit consisting of devices T1 and T2. This output stage is protected against the MPUL of 5.5 V of its counterpart (Fig. 1). The circuit scheme is shown in conjunction with a CMOS driver circuit.

The protection circuit consists of devices T3 to T8 and is described below.

Device T3, having its gate at Vh, is always on. It acts as a current support to and from output VS0 during switching. The current to the output diminishes when VS0 - Vh - Vt. The full output level of Vh is not reached. For the down- going transition, T3 does a good job. It is fully on and allows switching at a satisfactory speed. The protective function is very good, as T3...