Browse Prior Art Database

Multiple Digital Signal Processor Circuit Cards for Tool Control Applications

IP.com Disclosure Number: IPCOM000036625D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 57K

Publishing Venue

IBM

Related People

Hammond, JH: AUTHOR [+3]

Abstract

A technique is described whereby multiple digital signal processor circuit cards are provided for attachment to industrial computers, such as the IBM 7552. The circuit cards are unique in that they provide the controlling power required by computational intensive and parallel processing applications found in motion control.

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Multiple Digital Signal Processor Circuit Cards for Tool Control Applications

A technique is described whereby multiple digital signal processor circuit cards are provided for attachment to industrial computers, such as the IBM 7552. The circuit cards are unique in that they provide the controlling power required by computational intensive and parallel processing applications found in motion control.

The multiple digital signal processor circuit cards provide environmental optimization for motion control. All programming is provided by the host system, such as the IBM 7552. A dedicated high- speed bus is used for communications. The concept enables up to twenty million floating point operations per second per processor to be performed and up to eight processors can be attached to a single 7552 bus.

Two motion considerations are addressed: a) the time required to process the control algorithm, as related to the speed of the control system and b) the speed required to communicate between hardware and software.

The concept is designed for attachment to products, such as the IBM 7552, which do not include multi-servo motion controls. Two digital signal processors (DSPs), as shown in the figure, reside on a single form-factor card to minimize slot utilization in the 7552.

The DSPs are capable of communicating to and from the host 7552 MICRO CHANNEL* architecture through an arbitrated and multiplexed local memory. This allows the system processor to communicate and control the parallel processing DSPs. Boot control circuitry is provided to hold the DSP in reset so that the system processor can load and configure the DSP application software at system start-up time. This eliminates the need for on-card read-only memory.

An arbitrated and multi-buffered global memory area exists between a given DSP and all other DSPs, thereby providing an efficient high-speed communications link. The physical memory, consisting of a global memory, is distributed equally among all DSPs in the system. This...