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Clock Switching Mechanism for Asynchronous Access to DMA Storage Buffers

IP.com Disclosure Number: IPCOM000036627D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Bailey, RN: AUTHOR [+3]

Abstract

Disclosed is a mechanism which provides three independently operating circuits access to a DMA storage buffer.

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Clock Switching Mechanism for Asynchronous Access to DMA Storage Buffers

Disclosed is a mechanism which provides three independently operating circuits access to a DMA storage buffer.

A block diagram of the overall circuit is shown above. A multi- port register file, having one write port and one read port, serves as the DMA storage buffer. The write controls and data inputs on write port 1, along with the read controls on read ports 1, are multiplexed between the asynchronous circuits which need access to the DMA buffer. The DMA buffer controller manages this access by tracking the state of the buffers, and makes the appropriate connections to fill and empty the buffer as needed. The buffer is built using a ping-pong arrangment of register files, increasing transfer performance by allowing one circuit to fill one register file while the other is being emptied, and vice versa.

After power-on reset, the circuit is placed in the receive state. In this state, the DMA buffer controller switches the write port multiplexers (MUXs) to pass the receive circuit controls to the buffer, and the read port MUXs to pass the system interface circuit controls to the buffer. In this configuration the buffer is set up to take data from the receive circuit, store it in the buffer, and pass it to the system interface circuit, where it is transferred back to system main storage. The receive state is the default state of the device, which provides the advantage of being able to accept received frames without first preparing their path into the...