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Intelligent Pseudo Oscillator for Testability

IP.com Disclosure Number: IPCOM000036634D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 66K

Publishing Venue

IBM

Related People

Luckett, GC: AUTHOR [+4]

Abstract

With rapid improvements in design and simulation tools, designers are able to use an automatic logic synthesizer to create a circuit design which satisfies logic functions. Unfortunately, it may create testability problems, e.g., untested faults occur in the circuits. In some cases, aggressive circuit designers design a high performance or low cost circuit with tradeoffs which violate LSSD design rules. As a result, the circuits run well in the functional mode but fail in the testing environments.

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Intelligent Pseudo Oscillator for Testability

With rapid improvements in design and simulation tools, designers are able to use an automatic logic synthesizer to create a circuit design which satisfies logic functions. Unfortunately, it may create testability problems, e.g., untested faults occur in the circuits. In some cases, aggressive circuit designers design a high performance or low cost circuit with tradeoffs which violate LSSD design rules. As a result, the circuits run well in the functional mode but fail in the testing environments.

To ensure the quality of products, a direct approach seems to be a circuit redesign. However, this approach is usually expensive and may delay the product shipping schedule. In this invention, an alternative solution which eliminates the requirements of circuit redesign or silicon overheads is described. An "intelligent pseudo oscillator" (IPO) is used to increase the testability of the circuit without any additional cost of hardware.

(Image Omitted)

A dual-port L2 latch, as shown in Fig. 1, is used for illustration.

A test pattern was generated to detect a fault on the same chip as L2 but it is logically independent of L2. This test pattern accidentally turns on C2 and C3 clocks simultaneously. A "1" from the remote L1 (D2) forces node K2 low enough to pull node H1 down. The data in the L1 latch switches from a "1" to a "0." When the data is scanned out, the error occurs.

To fix this problem, one could add additional devices to force C2 to a "0" as C3 is a "1" or redesign the chip to prevent this from happening. However, this will increase the cost of products and delay shippi...