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Method to Improve the Performance of the Data Encryption Algorithm

IP.com Disclosure Number: IPCOM000036637D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 36K

Publishing Venue

IBM

Related People

Comba, PG: AUTHOR

Abstract

Disclosed is a method to speed up the execution of the Data Encryption Algorithm (DEA) [*] when implemented on a 16-bit processor such as the IBM Personal Computer (PC). The method requires replacing the "Initial Permutation" of the DEA by one of a class of Modified Initial Permutations; likewise, the "Final Permutation" is replaced by a Modified Final Permutation.

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Method to Improve the Performance of the Data Encryption Algorithm

Disclosed is a method to speed up the execution of the Data Encryption Algorithm (DEA) [*] when implemented on a 16-bit processor such as the IBM Personal Computer (PC). The method requires replacing the "Initial Permutation" of the DEA by one of a class of Modified Initial Permutations; likewise, the "Final Permutation" is replaced by a Modified Final Permutation.

When the DEA is implemented in software, the most time-consuming part is the "Rounds", which are executed 16 times. Each Round operates on 32 bits and consists of 8 separate substitutions, referred to as the S-boxes; each S-box has 6 bits of input and 4 bits of output. The S-boxes are usually combined with "Wire-Crossing Permutation" and implemented by table lookup. The S-boxes may also be combined in alternate pairs: (1,3), (5,7), (2,4) and (6,8); this results in 4 tables, each containing 4096 4-byte entries.

In a 16-bit processor, the 32 bits operated on in the Rounds are normally held in two 16-bit registers. If the input to the Rounds is as specified by the standard Initial Permutation, it is necessary, between the odd S-box pairs and the even S- box pairs, to rotate the 32 bits by 4 positions, and to exchange 2 bits between the two 16-bit registers. On an IBM PC this requires 12 instructions. This number of instruction can be reduced to 5 if the input to the Rounds is rearranged to one of the Modified Initial Permutations defined below.

The class of Modified Initial Permutations is defined in two stages: First, the Preferred Modified Initial Permutation is exhibited, then the other Modified Initial Permutations are defined in terms of the Preferred one. Let the 64-bit output of the standard Initial Permutation be represented by the bits indexed with the integers 0 through 63. Then the Preferred Modified Initial Permutation consists of the bits arranged as shown in the figure below.

The other Modified Initial Permutations are obtained from the Preferred one by permuting the columns in the fig...