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FIFO Buffers and Synchronized Address Generation Circuit

IP.com Disclosure Number: IPCOM000036643D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 4 page(s) / 85K

Publishing Venue

IBM

Related People

Davis, GT: AUTHOR [+4]

Abstract

This article describes a technique of using channel counters synchronized to a T-1 line or other time division multiplexed carrier system to control cycle-steal transfer of data samples between a network interface and RAM array. (Image Omitted)

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 46% of the total text.

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FIFO Buffers and Synchronized Address Generation Circuit

This article describes a technique of using channel counters synchronized to a T-1 line or other time division multiplexed carrier system to control cycle-steal transfer of data samples between a network interface and RAM array.

(Image Omitted)

In order to reduce the real-time performance constraints on this interface, it is desirable to add a first-in, first-out (FIFO) buffer in the data path. This allows data transfers to be slowed down at times to allow for other tasks to use the bus. The network interface then will no longer require a processor bus cycle at every instant a new byte of data is transferred on the network interface. As long as the average number of bus cycles available to the interface is greater than the average number of transfers required at the interface, the FIFO buffer will balance out short intervals of high bus activity by storing multiple bytes of data. For receive, the FIFO buffer will transfer data out faster than the network interface data rate in order to empty the FIFO buffer after accumulating multiple bytes due to excess bus traffic. The transmit FIFO buffer will load data into the FIFO buffer ahead of time in anticipation of future time-slots when the bus might be busy.

The buffering process in the FIFO buffer creates an additional problem at the cycle-steal RAM interface of the FIFO buffer. A time division multiplexing (TDM) channel counter is used to generate addresses for the cycle-steal transfers of data into the RAM. However, when using a FIFO buffer, the channel counter is not pointing to the channel which is being loaded or unloaded at the RAM interface, but rather points to the active channel at the network side of the FIFO buffer. Fig. 1 illustrates how this problem is handled by providing a Tx offset counter circuit 1, which is used to offset the Tx channel counter 2 via a full adder circuit 3. For receive, the cycle-steal transfer to RAM may occur after the channel counter has incremented beyond that channel. Therefore, the offset count from counter 4 must be subtracted from the channel counter 5 count. This may be handled by using a twos complement of the offset count in conjunction with a standard adder 6.

The adders 3 and 6 perform modulo 32 arithmetic, and provide the required function for the European frame format which has 32 channels, as well as for a high speed data link (HSDL) mode which redefines channel numbers relative to RAM addressing to permit modulo 32 operation. In the North American frame formats, however, channelized frames require calculation of the offset address using modulo 24 arithmetic. Modulo 24 circuits 7 and 8 use the standard adder outputs to compute the required modifications to the most significant two bits of the address. The two most significant bits of the five-bit adder output along with the carry out bit from the adder are required by the modulo 24 circuits.

Figs. 2A and 2B illustrate the detai...