Browse Prior Art Database

DCS Output Channel Receiver

IP.com Disclosure Number: IPCOM000036655D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Chu, SG: AUTHOR

Abstract

The channel receiver is designed to receive signals from ground down TTL logic chips and drive differential current switch (DCS) logic gates. The receiver can receive signal swings from -1.5 volts to 0 volts (ground), with threshold voltage at approximately -0.4 volt.

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DCS Output Channel Receiver

The channel receiver is designed to receive signals from ground down TTL logic chips and drive differential current switch (DCS) logic gates. The receiver can receive signal swings from -1.5 volts to 0 volts (ground), with threshold voltage at approximately -0.4 volt.

The circuit schematic is shown in the figure. T1 and T2 form an emitter- coupled current switch, with T1 as the input transistor and T2 as the reference transistor. T3, R4, R5 and R6 form a reference voltage generator which generates a stable reference voltage that is crucial to the operation of the receiver. T3 is used as a diode to minimize the reference voltage tolerance due to process parameter variations and power supply noise. This results in maximized noise margins for the receiver.

DCS outputs are complementary, but can be placed in an indeterminate state by faults such as current source opens and output shorts. Special test circuitry, which detects such faults, has been implemented in the receiver. The test circuitry is made up of 6 transistors and 2 resistors, namely, T7, T8, T9, T10, T11, T12, R9 and R10. When the faults are present and the output is in the indeterminate state, forcing a logic 1 to T0 or T1 will cause the output of the circuit to a determinate state and thus the fault can be detected.

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