Browse Prior Art Database

DCS Output Memory Receiver

IP.com Disclosure Number: IPCOM000036657D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Chu, SG: AUTHOR

Abstract

The memory receiver is designed to receive signals from CMOS memory chips and drive differential current switch (DCS) logic gates. The receiver can receive signal swings from -2.2 volts to +1.4 volts.

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DCS Output Memory Receiver

The memory receiver is designed to receive signals from CMOS memory chips and drive differential current switch (DCS) logic gates. The receiver can receive signal swings from -2.2 volts to +1.4 volts.

The circuit schematic is shown in the figure. T1 and T2 form an emitter- coupled current switch, with T1 as the input transistor and T2 as the reference transistor. The current source of the circuit is a current mirror which consists of T3, T4 and R3.

DCS outputs are complementary, but can be placed in an indeterminate state by faults such as current source opens and output shorts. Special test circuitry, which detects such faults, has been implemented in the receiver. The test circuitry is made up of 6 transistors and 2 resistors, namely, T7, T8, T9, T10, T11, T12, R8 and R9. When the faults are present and the output is in the indeterminate state, forcing a logic 1 to T0 or T1 will cause the output of the circuit to a determinate state and thus the fault can be detected.

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