Browse Prior Art Database

Trace Buffering System for Parallel Simulation of MP Systems

IP.com Disclosure Number: IPCOM000036658D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 43K

Publishing Venue

IBM

Related People

Darema-Rogers, F: AUTHOR [+6]

Abstract

Simulation at the instruction level of the execution of each CPU in a multiprocessor (MP) system is not just time consuming but is also very I/O intensive. One problem is where and how to efficiently store the huge volume of traces generated so that the whole simulation is not significantly delayed by the trace-writing step. This I/O demand from the base system grows at least linearly with the number of CPUs in the simulated MP system. A Trace Buffering System (TBS) is described below which frees the simulation from the number of I/O devices available and at the same time minimizes any I/O overheads during trace generation. For reasons of high volume and portability, tape is so far the only candidate to store traces of practical length. Therefore, it will be assumed that only tapes are used to store the traces.

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Trace Buffering System for Parallel Simulation of MP Systems

Simulation at the instruction level of the execution of each CPU in a multiprocessor (MP) system is not just time consuming but is also very I/O intensive. One problem is where and how to efficiently store the huge volume of traces generated so that the whole simulation is not significantly delayed by the trace-writing step. This I/O demand from the base system grows at least linearly with the number of CPUs in the simulated MP system. A Trace Buffering System (TBS) is described below which frees the simulation from the number of I/O devices available and at the same time minimizes any I/O overheads during trace generation. For reasons of high volume and portability, tape is so far the only candidate to store traces of practical length. Therefore, it will be assumed that only tapes are used to store the traces.

If the simulation is performed by a program that simulates one instruction per CPU on a round-robin basis, then the whole process is gated by the writing step. For example, even if I/O time and CPU time can be completely overlapped, the simulation time is at least the time taken to write the traces out to the tapes. On the other hand, if each CPU in the simulated MP system is traced by a separate simulation process (SP), multiple tape drives can be used to write the traces. This helps, but an I/O problem still exists, because I/O devices are in general not shareable across user programs in a normal system. If a tape drive is attached to each SP, then the number of CPUs simulated is limited by the number of tape drives actually available in the base system. On the other hand, if the existing file spooling system provided in the base system is used by sending the traces generated by a group of SPs to a writing process (WP) that writes the traces out to a tape, experiments have shown that, due to the additional I/O overhead from the spooling system, the WP is too slow to cope with more than one SP.

The present TBS is built within a parallel simulation to send traces from groups of SPs to a group of WPs in order to take advantage of the maximum parallelism (multiple CPUs and I/O devices) in a base system. It will be ass...