Browse Prior Art Database

Current Steering Diode Transistor Logic

IP.com Disclosure Number: IPCOM000036659D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Cavaliere, JR: AUTHOR [+2]

Abstract

It is proposed to improve the speed and power performance of diode transistor logic (DTL) circuits by providing a constant base current for the switching transistor. The improvement works to eliminate degradation in the switching speed of the circuit since more switching loads are connected at the output without an increase in power.

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Current Steering Diode Transistor Logic

It is proposed to improve the speed and power performance of diode transistor logic (DTL) circuits by providing a constant base current for the switching transistor. The improvement works to eliminate degradation in the switching speed of the circuit since more switching loads are connected at the output without an increase in power.

In conventional DTL (Fig. 1) the turn-on base current, IB, is less than the turn-off base current, ID . When more switching loads are connected at the output, the base drive current becomes insufficient and switching speed is adversely affected. While it is possible to increase the base drive, the additional discharging current required results in an increase in power dissipation.

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The proposed current steering diode transistor logic (CSDTL) (Fig. 2) achieves a higher performance than does the DTL without an increase in circuit power. In it, ID = IB . An ideal current source, which may be replaced by a lateral PNP device (Fig. 3) is used in simulation to provide a constant turn-on, turn-off current.

As compared to DTL, CSDTL has more base current, but less discharging or loading current. With its stronger base drive, switching speed is improved with no degradation occurring even at heavy loading conditions. For current switch emitter-follower (CSEF) circuit compatibility with VCC = 1.35 V, VT = -0.7 V, VEE = -1.7 V and ground, the CSDTL would be configured as indicated in Fig. 4...