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I/O Channel Controller System Bus Interface Unit Ack Signal Checker

IP.com Disclosure Number: IPCOM000036667D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 35K

Publishing Venue

IBM

Related People

Johnson, LE: AUTHOR

Abstract

This invention is a logic subsystem that times the arrival of, and tests the value of, the ack_ signal from the system bus master during address and data transmission protocols from the I/O Channel Controller (IOCC). The ack_ signal is an indication from the master that the address or data were received with no error.

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I/O Channel Controller System Bus Interface Unit Ack Signal Checker

This invention is a logic subsystem that times the arrival of, and tests the value of, the ack_ signal from the system bus master during address and data transmission protocols from the I/O Channel Controller (IOCC). The ack_ signal is an indication from the master that the address or data were received with no error.

The ack checker is part of the IOCC Bus Interface Unit (BIU) transmit logic. The BIU also includes a receive subsystem and an interrupt subsystem.

This implementation saves hardware by using one timing chain for both av_ and dv_ (see the figure). It also simplifies the transmit controller by accomplishing the checking function in parallel with other transmit functions.

Definition of signals:

Inputs

av_ Latched address valid signal from the

transmit controller. Signifies that the

dma address is active on the system bus.

dv_ Latched data valid signal from the

transmit con

troller. Signifies that data is valid on

the system bus.

lack_ Latched ack_ signal. Valid one cycle

following

ack_ on the system bus.

dma Bit from the transmit controller's

master status register that means that a

dma cycle is in progress or waiting for

system bus grant.

dma_err_ack Acknowledge signal from the IOCC dma

controller

after a dma address error has been

logged by this subsystem.

gmb_dperr Signal from the IOCC parity checking

logic that a

parity error has been detected.

Outputs

gmb_dma_aderr A dma address error has been detected by

this subsystem.

gmb_chk_stop A data error or sy...