Browse Prior Art Database

I/O Channel Controller System Bus Interface Unit Receive Controller

IP.com Disclosure Number: IPCOM000036669D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Johnson, LE: AUTHOR

Abstract

Disclosed is a finite state machine that provides system interface handshaking and data-flow control signals to detect and process Programmed Input/Output (PIO) load/store transactions from the system bus.

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I/O Channel Controller System Bus Interface Unit Receive Controller

Disclosed is a finite state machine that provides system interface handshaking and data-flow control signals to detect and process Programmed Input/Output (PIO) load/store transactions from the system bus.

The receive controller is part of the I/O Channel Controller (IOCC) Bus Interface Unit (BIU), which also includes a transmit subsystem and an interrupt subsystem.

The implementation described here has the advantage that its state assignment is coded to accept the pio_cmp signal (see figure) asynchronously, saving hardware and increasing performance by eliminating a synchronizing latch. The validation of cycle parameters is done by separate logic, allowing the receive controller to start its sequencing in parallel with the validation function, and the receive controller can abort the cycle cleanly if the parameter checks fail. A separate counter is loaded and used to terminate system bus transactions after the correct number of cycles, further reducing the complexity of the controller implementation.

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