Browse Prior Art Database

I/O Channel Controller System Bus Interface Unit Buffer Pointers

IP.com Disclosure Number: IPCOM000036673D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR [+2]

Abstract

The subsystem described here implements the generation of read and write addresses for the DMA and PIO data buffers of the I/O Channel Controller (IOCC) such that the IOCC system Bus Interface Unit (BIU) may store and load data for system transactions.

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I/O Channel Controller System Bus Interface Unit Buffer Pointers

The subsystem described here implements the generation of read and write addresses for the DMA and PIO data buffers of the I/O Channel Controller (IOCC) such that the IOCC system Bus Interface Unit (BIU) may store and load data for system transactions.

In addition, this subsystem supports the simultaneous clearing of the DMA buffer while data is moved to system memory to ensure data security, with the advantage that hardware is saved and performance increased because the zero- fill operation is performed in parallel with normal DMA write operations. The straightforward approach would use dedicated hardware or programmer intervention to accomplish clearing of the DMA buffers.

The IOCC contains buffers which hold data during transfers between the I/O bus and system memory. The I/O architecture allows multiple first party DMA masters on the I/O bus to access shared buffers within the IOCC. This means that two first party masters can use the same IOCC buffer when transferring data between system memory. However, these two masters might not be allowed to access each other's data segments. In cases like this, there are many ways one can provide data access security, but most of the obvious and classical approaches require either an increased latency in the data transfers or greater control hardware complexity. The "zero-fill" read approach was developed for the IOCC. This disclosure deals with the novel hardware implementation of the "zero- fill" concept.

The BIU Buffer Pointer subsystem consists of the following components: A four-bit binary counter controlled by the BIU

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