Browse Prior Art Database

Multiplier With Inverted or Buffered Columns

IP.com Disclosure Number: IPCOM000036674D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Dao-Trong, S: AUTHOR [+3]

Abstract

In a multiplier comprising lines receiving one operand and columns receiving another operand, the signals in the columns, having passed a number of lines, are inverted or buffered. If a column comprises a true and a complement signal, both signals are inverted or buffered after the same number of lines. In this way, only a small number of multiplier circuits switch simultaneously, reducing the amount of current noise.

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Multiplier With Inverted or Buffered Columns

In a multiplier comprising lines receiving one operand and columns receiving another operand, the signals in the columns, having passed a number of lines, are inverted or buffered. If a column comprises a true and a complement signal, both signals are inverted or buffered after the same number of lines. In this way, only a small number of multiplier circuits switch simultaneously, reducing the amount of current noise.

In a multiplier comprising two multiplying arrays, the column signals are applied in parallel to the leading lines of both arrays and are then inverted or buffered in either array. In this way, both arrays are simultaneously supplied with signals, increasing the performance of the multiplier.

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